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EN0-001 Exam Dumps : ARM Accredited Engineer

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ARM Accredited Engineer Questions and Answers

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Question 1

Which events would be counted using the Performance Monitoring Unit (PMU) in order to measure the data cache efficiency of an application?

Options:

A.

Memory read instructions, and memory write instructions

B.

Architecturally executed instructions, and instruction fetches causing a cache line refill

C.

Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

D.

Memory read or write operations causing a cache access, and architecturally executed instructions

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Question 2

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

Options:

A.

5 cycles

B.

7 cycles

C.

8 cycles

D.

15 cycles

Question 3

Which of the following is an optional extension to the ARMv7-A architecture?

Options:

A.

VFP

B.

The System Control Coprocessor (CP15)

C.

Support for memory barriers

D.

A Memory Protection Unit conforming to the PMSA

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