EN0-001 Exam Dumps : ARM Accredited Engineer

Memory read instructions, and memory write instructions

Architecturally executed instructions, and instruction fetches causing a cache line refill

Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

Memory read or write operations causing a cache access, and architecturally executed instructions

Base address of the heap must be the same as the initial stack pointer.

Stack pointer must be 8-byte aligned.

Heap must be in external RAM.

Initial stack pointer must be the lowest addressable memory location.

A dual-core Cortex-A9 processor

A Cortex-R4 processor with a Cortex-M3 system controller

A Cortex-A8 processor with a graphics processing unit (GPU)

A uni-core Cortex-A5 processor with a digital signal processor (DSP)