EN0-001 Exam Dumps : ARM Accredited Engineer

FIQ exceptions must not be taken

The instruction cache must be enabled

Global variables must be initialized to zero

The Reset Vector must reside in non-volatile memory

It traps writes to the memory containing the vector table

It provides additional resources for debugging exception handlers

It provides configurable exception priorities on an ARM processor

It provides an improved mechanism for an application to handle exceptions

Memory read instructions, and memory write instructions

Architecturally executed instructions, and instruction fetches causing a cache line refill

Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

Memory read or write operations causing a cache access, and architecturally executed instructions