EN0-001 Exam Dumps : ARM Accredited Engineer

Memory-mapped registers.

Generic Interrupt Controller (GIC) registers.

Debug Coprocessor Registers (CPU).

System Control Coprocessor Registers (CP15).

Memory read instructions, and memory write instructions

Architecturally executed instructions, and instruction fetches causing a cache line refill

Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

Memory read or write operations causing a cache access, and architecturally executed instructions

±32MB

±4MB

±12KB

±4KB